Integration of high voltage lateral MOS devices in low voltage C

Details Integration of high voltage lateral MOS devices in low voltage C Integration of high voltage lateral MOS devices in low voltage C

1992-05-12

1994-06-21

Thomas, Tom

Fishing, trapping, and vermin destroying

437 40, 437 44, 437 51, 437 54, 437 56, H01L 2170

Patent

active

053228049

ABSTRACT:
Region forming steps or interconnect-forming steps through which low voltage CMOS devices are formed in a semiconductor wafer are also employed to simultaneously form one or more regions or layers at selected sites of a substrate where high voltage devices are to be formed. Such selective modification of an already existing mask set designed for low voltage CMOS topography allows additional doping of the substrate or provision of further overlay material to accommodate the effects of high voltage operation of selected areas of the water and thereby effectively performs precursor tailoring or modification of those portions of the wafer where a high voltage condition will be encountered.

REFERENCES:
patent: 4285116 (1981-08-01), Meguro
patent: 4403395 (1983-09-01), Cunnan
patent: 4795716 (1989-01-01), Yilmaz et al.
patent: 4823173 (1989-04-01), Beasom
patent: 4914051 (1990-04-01), Huie et al.
patent: 5024962 (1991-06-01), Murray et al.

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