Patent
1985-03-14
1987-03-31
Edlow, Martin H.
357 40, 357 68, 357 45, H01L 2702
Patent
active
046546898
ABSTRACT:
A semiconductor device comprises a first circuit section positioned in a center portion of the substrate, a second circuit section provided in the peripheral portion of the substrate, and first to third power supply main wiring layers on the substrate. The first wiring layer supplies a first voltage such as ground potential to the second circuit section. The second wiring layer supplies a second voltage such as Vcc potential to the second circuit section. The third wiring layer supplies the first voltage to the first circuit section. The device further comprises a MOS type capacitor having upper and lower electrodes. The upper electrode of the capacitor is connected to the second wiring layer, and the lower electrode of the capacitor is connected at its end parts to the first and third wiring layers such that both wiring layers are electrically connected each other. Such a device can decrease the surge current induced in the wiring layers by the capacitor. Further, signal lines can be continuously formed with low electrical resistance on an insulating layer above the capacitor. Therefore, the access time of the device can be reduced.
REFERENCES:
patent: 4168442 (1979-09-01), Satou et al.
patent: 4454529 (1984-06-01), Philofsky et al.
patent: 4553050 (1985-11-01), Feinberg et al.
Crane Sara W.
Edlow Martin H.
NEC Corporation
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