Semiconductor memory device including memory cells connected to

Details Semiconductor memory device including memory cells connected to Semiconductor memory device including memory cells connected to

1993-09-27

1995-01-03

LaRoche, Eugene R.

Static information storage and retrieval

Interconnection arrangements

365 51, G11C 506

Patent

active

053792475

ABSTRACT:
A memory cell array in a static random access memory (SRAM) includes an improved circuit. Memory cells in one row are connected to a ground line. The memory cells in another row are connected to the ground line. Word lines each are connected alternately to the memory cells of two rows column by column. In a read operation, when one of the word lines is activated, a current flows from the memory cell to the two ground lines. Since a total of currents flowing through one ground line is reduced, the rise of potentials of the ground lines is prevented, so that destruction of data can be prevented.

REFERENCES:
patent: 4733374 (1988-03-01), Furuyama et al.
patent: 5289404 (1994-02-01), Okamoto
Y. Kobayashi et al. "A 10-.mu.WStandby Power 2.56K CMOS SRAM" IEEE Journal of Solid-State Circuits, vol. 20, No. 5, Oct. 1985, pp. 935-940.
D. Min et al. "Wordline Coupling Noise Reduction Techniques For Scaled DRAMs" 1990 Symposium on VLSI Circuits, Jun. 1990, pp. 81-82.
"A Polysilicon Transistor Technology for Large Capacity SRAMs", by Shuji Ikeda et al, International Electron Devices Meeting, Dec. 9-12, 1990, pp. 469-472.

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