Structure and method for mounting semiconductor devices, and liq

Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only

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Details

345150, 345151, G02F 11345

Patent

active

058936238

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

This invention relates to a structure and method or mounting semiconductor devices and, more particularly, to a structure and method suitable for mounting semiconductor devices in an electronic apparatus, such as a liquid crystal display, by using a circuit board. Further, this invention relates to a liquid crystal display in which semiconductor devices for driving the liquid crystal display are mounted by using such a structure and method.


BACKGROUND ART

In the prior art, there are known methods for mounting semiconductor devices in an electronic apparatus. For example, there is a so-called TAB (Tape Automated Bonding) method for connecting tape carrier packages, on each of which semiconductor devices are mounted, in a bundle as a single connection by using TAB technology, and a COG (Chip-on-Glass) method for directly connecting semiconductor devices to interconnecting wires or lines, the pattern of which is formed on a glass substrate.
In the case of a liquid crystal display, it is typical to connect a driving semiconductor chip to the peripheral part of the panel of the liquid crystal display, which consists of X-electrodes and Y-electrodes of a matrix structure, by using the TAB method. However, in this case, input and output lines of semiconductor devices are formed on a same surface of a TAB package. Moreover, each TAB package is mounted on the outside of the liquid crystal panel. Thus, the mounting area becomes very large. This results in a large frame portion (commonly referred to as a "large death area") formed about the peripheral part of the liquid crystal display panel. Consequently, the liquid crystal display has a problem in that the entire liquid crystal display is large in size and the displaying area is relatively small.
Furthermore, a separate driving circuit board provided with an input bus line for supplying an input signal and electric power to the semiconductor devices of each TAB package is necessary. Thus, the liquid crystal display has a problem in that the death area is further expanded and the cost increases.
Moreover, in the case of directly mounting the driving semiconductor devices on the surface of the liquid crystal panel by using the COG method, the patterns of the input and output lines or the like are formed on the surface of the peripheral part of the liquid crystal panel. As a result, the mounting area of the liquid crystal panel becomes large. Similarly, as in the case of employing the TAB method, the death area becomes very large. Additionally, the liquid crystal panel is furnished with the input and output lines and the input bus line crosswise on a same surface. Consequently, the liquid crystal display has a problem in that the manufacturing cost becomes very high.
Therefore, the applicant of the instant application proposed a structure in which a liquid crystal driving LSI is mounted in a liquid crystal display through a multilayer circuit board, as described in the specification of Japanese Patent Application No. 5-2235223/1993. As illustrated in FIGS. 26 and 27, this arrangement includes a laminated circuit board 55 having an input line 57, an output line 58, and an input terminal 59 formed on a surface thereof to a predetermined position at which a driving LSI 56 is connected. An output terminal 62 for connecting a liquid crystal panel 60 to a connecting terminal 61 is formed on the back surface of the circuit board. Input bus lines 63 or the like are provided in intermediate layers. Interlayer connections are established between the output line and terminal and between the input line and terminal through a via hole 64.
With this arrangement, a driving circuit board connected to the TAB board becomes unnecessary. Consequently, the mounting area is small, and the entire liquid crystal display can be made small and thin. Furthermore, reliability is improved by reducing the number of connection points.
This laminated circuit board, however, has the following problems. Manufacturing cost becomes high because interlayer connections are made among

REFERENCES:
patent: 5117300 (1992-05-01), Wiemer
patent: 5402255 (1995-03-01), Nakanishi et al.
patent: 5467210 (1995-11-01), Kishigami
patent: 5668700 (1997-09-01), Tagusa et al.
patent: 5670994 (1997-09-01), Kawaguchi et al.

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