Methods for automatically pipelining loops

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

364578, 364488, 364489, 364490, G06F 9455

Patent

active

057649510

ABSTRACT:
A method and an apparatus for creating a representation of a circuit with a pipelined loop from an HDL source code description. It infers a circuit including a pipelined loop which has cycle level simulation behavior matching that of the source HDL. Loop carry dependencies and memory and signal I/O accesses within the loop are scheduled correctly.

REFERENCES:
patent: 4827427 (1989-05-01), Hyduke
patent: 5111413 (1992-05-01), Lazansky et al.
patent: 5128871 (1992-07-01), Schmitz
patent: 5237513 (1993-08-01), Kaplan
patent: 5274793 (1993-12-01), Kuroda et al.
patent: 5437037 (1995-07-01), Furuichi
patent: 5544066 (1996-08-01), Rostoker et al.
patent: 5572437 (1996-11-01), Rostoker et al.
Alexander Aiken et al. "Optimal Loop Parallelization," Proceedings of the SIGPLAN '88 Conference on Programming Language Design and Implementation, Atlanta, GA, Jun. 1988, pp. 308-317.
Raul Camposano, "Design Process Model in the Yorktown Silicon Compiler," Proceedings of the 25th ACM/IEEE Design Automation Conference, 1988, pp. 489-494.
Brian Ebert et al., "SeeSaw: A Verilog Synthesis Viewer," 2nd Annual International Verilog HDL Conference. Design Excellence for Today and Tomorrow; Santa Clara, CA, Mar. 2, 1993, pp. 55-60.
Phillip B. Gibbons et al., "Efficient Instruction Scheduling for a Pipelined Architecture," 1986, pp. 11-16.
Brent Gregory et al., "ISIS: A System for Performance Driven Resource Sharing," Proceedings of the 29th ACM/IEEE Design Automation Conference, Jun. 1992, pp. 285-290.
Seongsoo Hong et al., "Compiling Real-Time Programs into Schedulable Code," ACM/SIGPLAN, Jun. 1993, pp. 166-176.
Michael C. McFarland et al., "The High-Level Synthesis of Digital Systems," Proceedings of the IEEE, vol. 78, No. 2, Feb. 1990, pp. 301-318.
Monica Lam, "Software Pipelining: An Effective Scheduling Technique for VLIW Machines," Proceedings of the SIGPLAN '88 Conference on Programming Language Design and Implementation Atlanta, GA, Jun. 1988, pp. 318-328.
Monica Sin-Ling Lam, "A Systolic Array Optimizing Compiler," May 1987, pp. 1-138.
Nohbyung Park et al., "SEHWA: A Program for Synthesis of Pipelines," 23rd Design Automation Conference/IEEE, 1986, pp. 454-460.
B. R. Rau et al., "Register Allocation for Software Pipelined Loops," ACM SIGPLAN, 1992, pp. 283-299.
Leon Stok, "False Loops through Resource Sharing," IEEE, 1992, pp. 345-348.
"Optimal Loop Parallelization" Alexander Aiken, 1988 ACM, pp. 308-317.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Methods for automatically pipelining loops does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods for automatically pipelining loops, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for automatically pipelining loops will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2213211

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.