Multi-byte processing of byte-based image data

Details Multi-byte processing of byte-based image data Multi-byte processing of byte-based image data

1996-03-27

1998-06-09

Chang, Jon

Image analysis

Applications

Motion or velocity measuring

382236, 382304, G06T 720

Patent

active

057647879

ABSTRACT:
Consecutive pixel values are loaded into the fields of a register. The data stored in the register is then transformed by operating on the register with one or more instructions that treat multiple pixel values as if they were single values. In a preferred embodiment, subsampled motion estimation processing is implemented on SIMD architecture. Values for consecutive pixels are loaded into the 8-bit fields of a SIMD register with a single byte-based SIMD load instruction. The contents of the register are then processed by applying one or more word-based SIMD instructions to the register which treat the data in the registers as 16-bit values. This word-based processing preferably results in sums of squares of differences between reference and target pixels used in motion estimation processing. Although the byte-based SIMD load instruction loads unwanted pixels (i.e., those pixels not selected for subsampled motion estimation processing) along with the desired pixels, the subsequent word-based SIMD processing treats the unwanted pixels as low-order bits of the desired pixels. The squares of differences may have errors, but the magnitudes of the errors are insignificant compared to the overall block comparison values and, as such, produce negligible if any affect on the selection of reference blocks during motion estimation processing.

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Toyokura et al. "A Video DSP with a Macroblock-Level-Pipeline and a SIMD Type Vector-Pipeline Architecture for MPEG2 CODEC." IEEE Journal of Solid-State Circuits, vol. 29, No. 12, pp. 1474-1481, Dec. 1994.

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