Synchronous semiconductor memory device which allows switching o

Details Synchronous semiconductor memory device which allows switching o Synchronous semiconductor memory device which allows switching o

1996-10-22

1998-06-09

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

36523003, 365219, 365221, 36518905, 365 51, G11C 800

Patent

active

057645906

ABSTRACT:
A synchronous DRAM includes a selector which supplies 2 bits of serial data signals from one data input/output terminal to two input/output line pairs as parallel data signals in x8 configuration mode, and supplies 2 bits of parallel data signals from both data input/output terminals directly to two input/output line pairs in x16 configuration mode. Therefore, the synchronous DRAM allows switching of bit configuration, and it takes 2-bits prefetch configuration in x8 configuration mode, and signal pipeline configuration in x16 configuration mode.

REFERENCES:
patent: 5596541 (1997-01-01), Toda
Y. Takai, et al, "250Mbyte/sec Synchronous DRAM Using a 3-Stage-Pipelined Architecture," 1993 Symposium on VLSI Circuit, pp. 59-60.
Yunho Choi, et al, "16Mbit Synchronous DRAM with 125Mbyte/sec Data Rate," 1993 Symposium on VLSI Circuit, pp. 65-66.

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