Low voltage one transistor flash EEPROM cell using Fowler-Nordhe

Details Low voltage one transistor flash EEPROM cell using Fowler-Nordhe Low voltage one transistor flash EEPROM cell using Fowler-Nordhe

1995-09-27

1997-03-25

Nguyen, Viet Q.

Static information storage and retrieval

Floating gate

Particular biasing

365218, 36518521, 36518518, 36518528, G11C 700, G11C 1300

Patent

active

056151470

ABSTRACT:
A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

REFERENCES:
patent: 5274599 (1993-12-01), Ema
patent: 5357463 (1994-10-01), Kinney
patent: 5371706 (1994-12-01), Krentz et al.
patent: 5408431 (1995-04-01), Challa
patent: 5428578 (1995-06-01), Kaya et al.
patent: 5483485 (1996-01-01), Maruyama
patent: 5508959 (1996-04-01), Lee et al.

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