Multiplying apparatus

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Details

364754, G06F 752

Patent

active

056151411

ABSTRACT:
A multiplying apparatus, capable of processing in relatively high speed with relatively small hardware quantity, in which the circuits for relative-digits are composed of adders 1a, 1b, 1c, 1d, first D-flip flops 3a, 3b, 3c, 3d propagating the respective digits of a multiplier while latching them successively in synchronism with the clock CLK, second D-flip flops 2a, 2b, 2c, 2d latching either the respective additional results of the adders of the digits of themselves or the respective additional results of the adders of the next digits according to respective values being latched by the first D-flip flops 3a, 3b, 3c, 3d in synchronism with the clock CLK, and delay circuits 5a, 5b, 5c delaying the propagation of the clock CLK to the next digit until the adders 1a, 1b, 1c, 1d for the respective digits output the respective carries, in other words, until the adders 1a, 1b, 1c, 1d finish the respective additional operations.

REFERENCES:
patent: 3805043 (1972-10-01), Clary
patent: 5262975 (1993-11-01), Ohki
patent: 5325321 (1994-06-01), Ishida
patent: 5337268 (1994-08-01), Kojima
patent: 5457646 (1995-10-01), Jang et al.

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