Fixed-point arithmetic unit

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39542102, G06F 748, G06F 934

Patent

active

056151403

ABSTRACT:
A fixed-point arithmetic unit has a calculation controller for detecting number of significant bits of data to be calculated and controlling an adder so as to inhibit it from transferring a carry to a portion of the adder unnecessary for calculation of the significant bits and a register controller for controlling a register adapted to store input and output of the adder such that only the significant bits of data are stored in the register, whereby when the significant bits of data is smaller than a bit width of the arithmetic circuit, consumptive power of the arithmetic unit can be reduced.

REFERENCES:
patent: 3331056 (1967-07-01), Lethin et al.
patent: 5081607 (1992-01-01), Bates et al.
patent: 5189636 (1993-02-01), Patti et al.
patent: 5210839 (1993-05-01), Powell et al.
patent: 5237672 (1993-08-01), Ing-Simmons et al.
patent: 5390135 (1995-02-01), Lee et al.
patent: 5404474 (1995-04-01), Crook et al.

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