Power reducing buffer/latch circuit

Details Power reducing buffer/latch circuit Power reducing buffer/latch circuit

1991-10-10

1993-02-23

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307481, 307453, H03K 19096, H03K 1920

Patent

active

051893193

ABSTRACT:
A data latch/buffer cell for driving a data bus line conditionally precharges the line only during cycles prior those in which data is actually sampled. An input gate selectively enables a data input signal for application to a latching circuit. Prior to application of the data input, a conditional precharge signal is applied to the latch circuit to clear the previously latched data. A latch circuit is coupled to the gate of a pull-down transistor which drives the data bus. The conditional precharge signal is also coupled to the gate of a complementary pull-up transistor to precharge the bus line. Application of the conditional precharge signal to the gate of the pull-up transistor is delayed relative to turning off the pull-down transistor to preclude a rush through current in the driver.

REFERENCES:
patent: 4451745 (1984-05-01), Itoh et al.
patent: 4496852 (1985-01-01), Blaser et al.
patent: 4700086 (1987-10-01), Ling et al.
patent: 4876465 (1989-10-01), Podkowa et al.
patent: 4983860 (1990-01-01), Yim et al.
patent: 5003501 (1991-03-01), Podkowa

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