Stepdown voltage generator having active mode and standby mode

Details Stepdown voltage generator having active mode and standby mode Stepdown voltage generator having active mode and standby mode

1991-05-31

1993-02-23

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072966, 307359, 323314, H03K 301

Patent

active

051893169

ABSTRACT:
In an active mode, a transistor 61 or 63 is turned on, so that a reference voltage generator circuit 1 and an internal voltage correcting circuit 2 are activated. Consequently, an internal voltage V.sub.INT which is stepped down is applied to an internal main circuit 7. Conversely, in a standby mode, a transistor 61 or 63 is turned off, so that the reference voltage generator circuit 1 and the internal voltage correcting circuit 2 are inactivated. Consequently, the current does not flow in the reference voltage generator circuit 1 and the internal voltage correcting circuit 2, resulting in reduction of a consumption power. Simultaneously, a transistor 62 or 64 is turned on, so that a source voltage Ext.Vcc is directly applied to the internal main circuit 7 through the transistor 62 or 23. Thereby, operation conditions of logic circuits in the internal main circuit 7 are maintained.

REFERENCES:
patent: 4649291 (1987-03-01), Konishi
patent: 4691123 (1987-09-01), Hashimoto
patent: 4724339 (1988-02-01), Ishida
patent: 4833341 (1989-05-01), Watanabe et al.
"VLSI-Oriented Voltage Down Converter with Sub-Main Configuration", Takayasu Sakurai et al., 16th Int. Conf. Solid State Devices and Materials (1984) Kobe, Aug. 30-Sep. 1, pp. 74-75.
Furuyama et al., "A New On-Chip Voltage Converter for Submicrometer High-Density DRAM's," IEEE Journal of Solid-State Circuits, vol. SC-22, No. 3, Jun. 1987, pp. 437-441.
Hayakawa et al., "A Process-Insensitivity Voltage Down Converter Suitable for Half-Micron SRAM's," 1988 Symposium on VLSI Circuits, Digest of Technical Papers, Aug. 1988, pp. 53-54.
Horiguchi et al., "Dual-Operating-Voltage Scheme for a Single 5-V 16-Mbit DRAM," IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988.

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