Nitride polish stop for forming SOI wafers

Details Nitride polish stop for forming SOI wafers Nitride polish stop for forming SOI wafers

1992-12-16

1993-11-16

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 68, 437947, 437981, 148DIG168, 156630, 156636, 156649, H01L 21302

Patent

active

052623467

ABSTRACT:
A method of forming a SOI integrated circuit includes defining thin silicon mesas by wet etching a device layer having the <100> orientation down to the underlying insulator so that the (111) crystal planes control the lateral etching, forming a nitride bottom polish stop in the bottom of the apertures by a low temperature CVD process, with nitride sidewalls on the (111) planes of the silicon mesas being susceptible to easy removal, so that no hard material is present during a chemical-mechanical polishing step to thin the device layer down to less than 1000 .ANG., and filling the apertures with a temporary layer of polysilicon to provide mechanical support to the edges of the device layer during the polishing operation.

REFERENCES:
patent: 3911562 (1975-10-01), Youmans
patent: 4408386 (1983-10-01), Takayashiki et al.
patent: 4735679 (1988-04-01), Lasky
patent: 4824795 (1989-04-01), Blanchard
patent: 4971925 (1990-11-01), Alexander et al.
patent: 5124274 (1992-06-01), Ohki et al.

Affiliated with

Also associated with

Rating

Nitride polish stop for forming SOI wafers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Nitride polish stop for forming SOI wafers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nitride polish stop for forming SOI wafers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-22046