Complimentary bipolar/CMOS fabrication method

Details Complimentary bipolar/CMOS fabrication method Complimentary bipolar/CMOS fabrication method

1992-05-15

1993-11-16

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

148DIG9, H01L 2170, H01L 2700

Patent

active

052623459

ABSTRACT:
A complementary bipolar process enables both PNP and NPN transistors to be added to a CMOS process with a minimum of extra fabrication steps. The P-well of a CMOS process is used for the collector region of the PNP transistor and the "down isolation" for the NPN transistor. A buried P diffusion provides "up" isolation for the NPN transistor and buried collector for the PNP transistor. A method for increasing the NPN buried collector to "up" isolation breakdown voltage is described which uses multiple N type impurities.

REFERENCES:
patent: 4637125 (1987-01-01), Iwasaki et al.
patent: 4721684 (1988-01-01), Musumeci
patent: 4927776 (1990-05-01), Soejima
patent: 4954456 (1990-09-01), Kim
patent: 5001073 (1991-03-01), Huie
patent: 5001076 (1991-03-01), Huie
Grebene, Alan B. "Bipolar and MOS Analog Integrated Circuit Design", A Wiley-Interscience Publication, John Wiley & Sons (1984), pp. 206-209.

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