Method of fabricating low leakage SOI integrated circuits

Details Method of fabricating low leakage SOI integrated circuits Method of fabricating low leakage SOI integrated circuits

1995-12-18

1997-03-25

Niebling, John

Fishing, trapping, and vermin destroying

437 34, 437 45, 437 56, 437 58, 437143, 148DIG77, 148DIG150, H01L 2170

Patent

active

056144334

ABSTRACT:
An SOI integrated circuit contains Al implanted below the channel areas of NFETs and has a positive substrate bias, the magnitude of the substrate bias and the implant dose being set such that the bias suppresses backside leakage in the PFETs and the implant dose suppresses leakage in the NFEts in spite of the bias.

REFERENCES:
patent: 3933530 (1976-01-01), Mueller et al.
patent: 3958266 (1976-05-01), Athanas
patent: 4507846 (1985-04-01), Ohno
patent: 4753895 (1988-06-01), Mayer et al.
patent: 4871690 (1989-10-01), Holonyak, Jr. et al.
patent: 4910160 (1990-03-01), Jennings et al.
patent: 4946799 (1990-08-01), Blake et al.
patent: 5024965 (1991-06-01), Chang et al.
patent: 5047356 (1991-09-01), Li et al.
patent: 5053353 (1991-10-01), Black
patent: 5231045 (1993-07-01), Miura et al.
patent: 5426062 (1995-06-01), Hwang
H. P. Zappe, et al., J. Electrochem. Soc., "Effective Charge Modification Between Si02 and Silicon", vol. 136, No. 8, Aug. 1989, pp. 2368-2370.
T. Miura, et al., 1988 VLSI Symposium, "Trench-Isolation Technology Using A1 Ion Implantation in a SIO2 Layer", pp. 19-20.

Affiliated with

Also associated with

Rating

Method of fabricating low leakage SOI integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating low leakage SOI integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating low leakage SOI integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2202962