Fishing – trapping – and vermin destroying
Patent
1995-10-23
1997-03-25
Niebling, John
Fishing, trapping, and vermin destroying
437193, 437247, H01L 21265
Patent
active
056144288
ABSTRACT:
A process and structure are disclosed for inhibiting the channeling of dopant through the polysilicon gate electrode into a semiconductor substrate during implantation of source and drain regions in the substrate during the formation of MOS devices. After deposition over a semiconductor substrate of a polysilicon layer which will be subsequently patterned to form a gate electrode, an amorphous layer of silicon is formed over the polysilicon layer. This amorphous silicon layer is then treated with a material such as a nitrogen-bearing material capable of inhibiting grain growth and recrystallization of the amorphous silicon during subsequent high temperature processing. The amorphous silicon and polysilicon layers are subsequently conventionally patterned to form the gate electrode. The structure is then implanted without channeling of the dopant ions through the gate electrode into the underlying portion of the substrate where the channel of the MOS device will be formed. The presence of the amorphous silicon over the polysilicon gate electrode inhibits the channeling of the implanted ions through the polysilicon layer, due to the amorphous (non-crystalline) structure of the amorphous silicon, while the treatment of the amorphous silicon with the material capable of inhibiting grain growth in the amorphous silicon prevents or inhibits the recrystallization of the amorphous silicon during subsequent processing before or during the implantation step to form the source and drain regions.
REFERENCES:
patent: 4897368 (1990-01-01), Kobushi et al.
patent: 5278096 (1994-01-01), Lee et al.
patent: 5364803 (1994-11-01), Lur et al.
patent: 5464792 (1995-11-01), Tseng et al.
Lebentritt Michael S.
LSI Logic Corporation
Niebling John
Taylor John P.
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