Patent
1994-07-13
1996-08-06
Harvey, Jack B.
39520021, G06F 1300
Patent
active
055443303
ABSTRACT:
An interconnect topology providing enhanced fault tolerance to a multi-component data processing system. The topology utilizes a plurality of rings for interconnecting multiple system components, or cards, at least two of which are indirectly connected so that communication therebetween is through a third component. Each of the system components is coupled to a set of at least two different rings and includes interface circuits for routing data and a bridge for permitting data to be transferred between the at least two rings.
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National Semiconductor, QR0001 Specification, Nov. 2, 1993, pp. 1-43.
Bither David S.
Loewy Charles S. F.
Wilson Paul C.
EMC Corporation
Harvey Jack B.
Travis John
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