Structure for contacting devices in three dimensional circuitry

Details Structure for contacting devices in three dimensional circuitry Structure for contacting devices in three dimensional circuitry

1985-11-22

1988-12-13

James, Andrew J.

357 234, 357 2312, 357 51, 357 55, H01L 2978

Patent

active

047914637

ABSTRACT:
The present invention is described in conjunction with the fabrication of a dRAM cell which an important application of the present invention. The described cell provides a one-transistor/one-capacitor dRAM cell structure and array in which the cell transistor is formed on the sidewalls of a substrate trench containing the cell capacitor; the word and bit lines cross over this trench. This stacking of the transistor on top of the capacitor yields a cell with minimal area on the substrate and solves a problem of dense packing of cells. One capacitor plate and the transistor channel and source region are formed in the bulk sidewall of the trench and the transistor gate and the other plate of the capacitor are both formed in polysilicon in the trench but separated from each other by an oxide layer inside the trench. The signal charge is stored on the polysilicon capacitor plate by an electrical connection of the source region with the polysilicon capacitor plate. The described embodiment provides an electrical connection which allows separate connection to the capacitor.

REFERENCES:
patent: 3893155 (1975-07-01), Ogiue
patent: 4199772 (1980-04-01), Natori et al.
patent: 4630237 (1986-12-01), Miura
patent: 4646118 (1987-02-01), Takemae
patent: 4649625 (1987-03-01), Lu
Sodini et al., "Enhanced Capacitance for One-Transistor Memory Cell", IEEE Trans. on Elec. Dev., Oct. 1976, pp. 1187-1189.
Chang et al., "Vertical FET Random-Access Memories with Deep Trench Isolation", IBM Tech. Disc. Bull., IBM Tech. Disc. Bull., vol. 22, No. 8B, Jan. 1980, pp. 3683-3687.
IBM Tech. Disc. Bull., "Dynamic RAM Cell with Merged Drain and Storage", vol. 27, No. 11, Apr. 1985, pp. 6694-6697.

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