Compact page-erasable eeprom non-volatile memory

Details Compact page-erasable eeprom non-volatile memory Compact page-erasable eeprom non-volatile memory

1994-07-12

1996-08-06

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular connection

36518531, 3651852, 36518508, 365 63, 365 72, 257316, 257321, 257322, G11C 1604

Patent

active

055441033

ABSTRACT:
A compact, electrically-erasable and electrically-programmable nonvolatile memory device employing novel programming and erasing techniques and using two layers of conductive or semiconductive material is disclosed. The memory cell of the present invention comprises a first layer serving as a floating gate and a second layer serving the functions of erasing the floating gate and of selecting the device for reading and programming the floating gate. The second layer may be made common to more than one memory device of the present invention. Programming of the device occurs by tunneling electrons into the first layer (floating gate) by hot-electron injection from a channel region controlled by the second layer. In one preferred embodiment of the present invention, erasure of the memory cell occurs by causing the tunneling of electrons from the first layer (floating gate) to the second layer by an enhanced tunneling mechanism. In this embodiment, the second layer preferably comprises a word line or row of a memory array. The erasure from the first layer (floating gate) to the second layer (word line) facilitates the providing of a compact, page-alterable non-volatile memory array. In a second preferred embodiment of the present invention, bit line coupling to the floating gate is used in place of the standard word-line coupling to the floating gate. The bit-line coupling also facilitates the providing of a compact, page-alterable non-volatile memory.

REFERENCES:
patent: 4326134 (1982-04-01), Owens et al.
patent: 4328565 (1982-08-01), Harari
patent: 4599706 (1986-07-01), Guterman
patent: 4639893 (1987-01-01), Eitan
patent: 4701776 (1987-10-01), Perlegos et al.
patent: 4783766 (1988-11-01), Samachisa et al.
patent: 4822750 (1989-04-01), Perlegos et al.
patent: 4855955 (1989-08-01), Cioaca
patent: 4868629 (1989-09-01), Eitan
patent: 4939690 (1990-07-01), Momodomi et al.
patent: 4959812 (1990-09-01), Momodomi et al.
patent: 4996669 (1991-02-01), Endoh et al.
patent: 5021847 (1991-06-01), Eitan et al.
patent: 5029130 (1991-07-01), Yeh
patent: 5045488 (1991-09-01), Yeh
patent: 5067108 (1991-11-01), Jenq
patent: 5172335 (1992-12-01), Sasaki et al.
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5202850 (1993-04-01), Jenq
patent: 5270979 (1993-12-01), Harari et al.
patent: 5313421 (1994-05-01), Guterman et al.
Guterman, et al., "An Electrically Alterable Nonvolatile Memory Cell Using A Floating-Gate Structure," IEEE Journal of Solid-State Circuits, vol. SC-14, No. 2, Apr. 1979.
R. Kazerounian, et al., "A 5 Volt High Density Poly--Poly Erase Flash EPROM Cell," Proceedings of the International Election Devices Meeting, Dec. 1988.
O. Bellezza, et al., "A New Self-Aligned Field Oxide Cell for Multimegabit EPROMS," Proceedings of the International Electron Devices Meeting, Dec. 1989.
B. J. Woo, et al., "A Novel Memory Cell Using Flash Array Contactless EPROM (FACE) Technology," Proceedings of the IEEE International Electron Devices Meeting, Dec. 1990.
J. Van Houdt, et al., "A 5-Volt-Only Fast-Programmable Flash EEPROM Cell with a Double Polysilicon Split-Gate Structure," Proceedings of the IEEE NVSM, Feb. 1991.
Philip J. Cacharelis, et al., "A Modular 1 um CMOS Technology Merging EEPROM, EPROM, and Interpoly Capacitors," Proceedings of the IEEE 11th NVSM, Feb. 1991.
Ali, et al., "A 50-ns 256K CMOS Split-Gate EPROM," IEEE Journal of Solid-State Circuits, vol. 23, No. 1, Feb. 1988.
Samachisa, et al., "A 128K Flash EEPROM Using Double-Polysilicon Technology," IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987.
Mukherjee, et al., "A Single Transistor EEPROM Cell and its Implementation in a 512K CMOS EEPROM," Proceedings of the IEDM, Dec. 1985.
Tam, et al., "A High Density CMOS 1-T Electrically Erasable Non-volatile (Flash) Memory Technology," Proceedings of the 1988.
Nakayama, et al. "A 5-V-Only One-Transistor 256K EEPROM with Page-Mode Erase," IEEE Journal of Solid-State Circuits, vol. 24, No. 4, Aug. 1989.
Masuoka, et al., "A New Flash E.sup.2 PROM Cell Using Triple Polysilicon Technology", Proceedings of the IEDM, Dec. 1984.
Wu, et al., "A Source-Side Injection Erasable Programmable Read-Only-Memory (SI-EPROM) Device," IEEE Electron Device Letters, vol. EDL-7, No. 9, Sep. 1986.
Mitzutani, et al., "A New-EPROM Cell With A Side-Wall Floating Gate for High-Density and High-Performance Device," Proceedings of the IEDM, Dec. 1985.
Chu, et al., "The Effect of Trench-Gate-Oxide Structure on EPROM Device Operation," IEEE Electron Device Letters, vol. 9, No. 6, Jun. 1988.
Seki, et al., "An 80-ns 1-Mb Flash Memory with On-Chip Erase/Erase-Verify Controller," IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct. 1990.
Komori, et al., "A High Performance Memory Cell Technology for Mega Bit EPROMS," Proceedings of the IEDM, Dec. 1985.
Lai, et al., "Design Of An E.sup.2 PROM Memory Cell Less than 100 Square Microns Using 1 Micron Technology," Proceedings of the IEDM, Dec. 1984.

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