Testable RAM architecture in a microprocessor having embedded ca

Details Testable RAM architecture in a microprocessor having embedded ca Testable RAM architecture in a microprocessor having embedded ca

1990-10-12

1993-09-28

Bowler, Alyssa H.

Boots, shoes, and leggings

364DIG1, 364240, 36424341, 395575, 365201, G06F 1300, G06F 1100, G11C 2900

Patent

active

052492818

ABSTRACT:
A microprocessor with embedded cache memory is disclosed. In a "test mode" of operation, caches are accessed directly from the memory interface signals. Direct writing and reading to/from the instruction and data caches allows the testing of the functionality of the cache memory arrays. External memory interface is granted to an external master via a bus arbitration mechanism so that the test mode operation can be utilized.

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patent: 4882673 (1989-11-01), Witt
patent: 4937738 (1990-06-01), Uchiyama et al.
patent: 4937781 (1990-06-01), Lee et al.
patent: 4945472 (1990-07-01), Sakamura et al.
patent: 4945512 (1990-07-01), DeKarske et al.

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