Circuit scale reduction for bit-serial digital signal processing

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G06F 738

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active

055440916

ABSTRACT:
For input signals f0-f7, by the implementing of signal processing in several stages with bit-serial form, output signals f0-f7 are obtained. For input signals f0-f7, non-two's power approximation proportions of ideal values of fixed coefficient, i.e., cos[.pi.l(2K+1)/2N] are applied. This results in asymmetrical hardware to implement a forward transform mode and an inverse transform mode. Therefore, by adding a circuit element which is employed for a forward transform mode, and by adding a circuit element which is employed for an inverse transform mode, hardware which can deal with both of forward transform and inverse transform is realized.

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