Process for making a hermetic low cost pin grid array package

Details Process for making a hermetic low cost pin grid array package Process for making a hermetic low cost pin grid array package

1987-10-05

1988-12-13

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437215, 29850, 174 5051, 174 525, 337 74, 361404, H01L 2348

Patent

active

047910755

ABSTRACT:
A process for making hermetic, low cost pin grid array (PGA) semiconductor die packages. The process involves die bonding a semiconductor die or integrated circuit chip to a substrate having an interconnect or metallization pattern thereon. The die is electrically connected to the pattern and then the die and the inner bonds are hermetically sealed inside a cap that is smaller than the substrate so that the ends of the metallization pattern are exposed. The leads are then electrically connected, such as by solder or other technique to the exposed ends of the pattern.

REFERENCES:
patent: 3634600 (1972-01-01), Griffin et al.
patent: 3673309 (1972-06-01), Dalmasso et al.
patent: 4382327 (1983-05-01), Bardens et al.
patent: 4423435 (1983-12-01), Test, II
patent: 4493143 (1985-01-01), Maier
patent: 4656442 (1987-04-01), Hayakawa

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