Nonvolatile memory device with compensation for over-erasing ope

Details Nonvolatile memory device with compensation for over-erasing ope Nonvolatile memory device with compensation for over-erasing ope

1993-11-26

1994-12-06

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

365 51, 365182, G11C 1300

Patent

active

053717040

ABSTRACT:
A groove is formed in a semiconductor layer, and a source region is formed at a part of the groove within the semiconductor layer. A control gate is buried via a first insulating layer within the groove. A floating gate is formed via a second insulating layer on the control gate. The floating gate extends over the first insulating layer. A drain region is formed within the semiconductor layer apart from the groove.

REFERENCES:
patent: 3660819 (1972-05-01), Frohman-Bentchkousky
patent: 4864374 (1989-09-01), Banertee
K. Naruke et al., "A New Flash-Erase EEPROM Cell with a Sidewall Select-Gate on Its Source Side", IEDM Tech. Digest, 1989, pp. 603-606.

Affiliated with

Also associated with

Rating

Nonvolatile memory device with compensation for over-erasing ope does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Nonvolatile memory device with compensation for over-erasing ope, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile memory device with compensation for over-erasing ope will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-219523