Dielectric relaxation correction circuit for charge-redistributi

Details Dielectric relaxation correction circuit for charge-redistributi Dielectric relaxation correction circuit for charge-redistributi

1991-06-27

1993-09-28

Logan, Sharon D.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341118, 341122, H03M 138, H03M 106

Patent

active

052489744

ABSTRACT:
This dielectric relaxation correction circuit for charge-redistribution A/D converters, which has a comparator 20 and operates in a sample, hold and conversion mode, comprises: a capacitor array 22, a replica capacitance 35, having a bottom plate, arranged so as to be subject to the same sequence of charging voltages that the array capacitors 22 experience but in a neutralizing manner such that an error in the capacitor array 22 voltage is neutralized by the same error in the replica capacitance 35, and; a sample and hold circuit (S/H) 36 for sampling an input signal voltage during the sample mode, wherein the sample and hold 36 is arranged to hold the bottom plate of the replica capacitance 35 at the input signal voltage. Other devices, systems and methods are also disclosed.

REFERENCES:
patent: 4574250 (1986-03-01), Senderowicz
patent: 4764753 (1988-08-01), Yukawa
patent: 4791405 (1988-12-01), Rybicki et al.
patent: 4803462 (1989-02-01), Hester et al.
patent: 4812817 (1989-03-01), Bernard
patent: 4851846 (1989-07-01), Haulin
patent: 4922252 (1990-05-01), Draxelmayr et al.
patent: 4999633 (1991-03-01), Draxelmayr

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