Semiconductor floor plan for a register renaming circuit

Details Semiconductor floor plan for a register renaming circuit Semiconductor floor plan for a register renaming circuit

1992-03-31

1994-12-06

Black, Thomas G.

Boots, shoes, and leggings

364488, 395800, G06F 1560

Patent

active

053716841

ABSTRACT:
A semiconductor floorplan layout for integrating a Data Dependency Checker (DDC) circuit and a Tag Assignment Logic (TAL) of a Register Renaming Circuit (RRC) circuit to conserve valuable semiconductor realestate. Floorplans of present invention contemplate laying out the DDC and TAL in such a fashion as to reduce the distance signals must travel between the DDC and TAL, as well as the distance signals must travel between the TAL and RPM. By rearranging selected DDC comparator rows and their associated TAL, a considerable amount of area can be conserved for performing register renaming for up to eight instructions.

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patent: 5276899 (1994-01-01), Neches
Luk, et al., "Multistack Optimization for Data-Path Chip Layout", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, No. 1, Jan. 1991.

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