Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1983-12-07
1986-03-11
Miller, Stanley D.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307246, 307270, 307259, 307585, H03K 1708
Patent
active
045756422
DESCRIPTION:
BRIEF SUMMARY
The present invention relates to a control circuit for an integrated device as set forth in the preamble of claim 1 and its application in a solid state relay.
For high voltage solid state relays with a high voltage switch on an integrated circuit there must be provided a galvanic isolation between the electronic switching paths and the control input of the relay. It is known to perform said galvanic isolation with the aid of opto-couplers or transformers. But neither opto-couplers nor transformers can be integrated in known MOS-technique on a single chip together with the high voltage part of the relay.
A galvanic isolation between the high voltage switch and the control input of the solid state relay is very important for a fully integrated circuit because the high voltage of the switch may damage the control portion of the relay or may at least result in an unintentional switching of the relay. The galvanic isolation between the control input and the output of the relay is desired or even required for many applications, e.g. for subscriber line circuits in telephony wherein the switch portion of the relay should be free of ground potential.
From U.S. Pat. No. 4,170,740 there is known an integratable solid state relay having galvanically isolated inputs and outputs. The galvanic isolation is performed by capacitors between a control circuit including a DC/DC-converter and a drive circuit with an EXCLUSIVE-OR gate being responsive to control signals in phase opposition only and by the gate capacitances of the MOS-transistors in the switch circuit between the load circuit and the logic circuit. This relay can be integrated without any problems, but its noise margin capability in its off-condition is very poor. This is caused by the fact that the complementary MOS-transistors in the switch are correctly brought into the conducting condition by a positive bias, that however the change into their blocked condition is performed only by dropping this bias. This results in different time constants for switching on and off and in a high impedance state-off condition so that there is a possibility that the gate capacitances are charged by spurious voltages from the load or the control circuits leading to an unintentional switching.
It is therefore an object of the present invention to provide a circuit arrangement for an integratable solid state relay which avoids the above mentioned drawbacks and which provides the same noise margin capability in both switching conditions.
This object is achieved by the invention as set forth in the characterizing part of claim 1. Preferred embodiments are set forth in the depending claims.
The invention will be best understood from the following description of embodiments taken in conjunction with the accompanying drawing in which:
FIG. 1-3 show circuit diagrams of asymmetrical MOS-switches to explain the mode of operation of switches of this kind;
FIG. 4 shows a circuit diagram of a symmetrical MOS-switch in its simplest form;
FIG. 5 shows a circuit diagram of the drive circuit of an integratable solid state relay according to the invention;
FIG. 6 shows a circuit diagram of the control circuit of the relay according to FIG. 5; and
FIG. 7 shows a circuit diagram of a simplified version of the drive circuit of a solid state relay.
As in the above mentioned patent also in the present solid state relay there are used capacitances for the galvanic isolation. The control is performed via DC/DC-converters and the load switches are MOS-transistors with double diffusion, i.e. DMOS-transistors with a high break-through voltage of about 400 V as it is needed for a wide application of the solid state relay. The technique of the double diffusion for achieving high break-through voltages was described by Dr. Plumer, Standford University in IEEE Journal Solid State Circuits, vol. SC-11, Dec. 1976, pages 809-817.
The DC/DC-converter as shown in FIG. 1 is a classical capacitively coupled voltage doubler with an AC-generator G.sub.1, capacitors C.sub.1 and C.sub.2, diodes D.sub.1 and D.sub.2 an
REFERENCES:
patent: 3564387 (1971-02-01), Gadberry
patent: 3777181 (1973-12-01), Bancroft
patent: 4156153 (1979-05-01), Szechenyi
patent: 4170740 (1979-10-01), Pernyeszi
patent: 4443719 (1984-04-01), Planer et al.
patent: 4487458 (1984-12-01), Janutka
patent: 4488058 (1984-12-01), Cheffer
Siebel, "Peripheral Devices for the Unimat 4080 PABX", Electrical Communication, vol. 55, No. 1, 1980 pp. 57-62 (179/18ES).
Hochreutiner Roger M.
Mattheus Walter
Hudspeth D. R.
International Standard Electric Corporation
Miller Stanley D.
Morris Jeffrey P.
O'Halloran John T.
LandOfFree
Control circuit for an integrated device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Control circuit for an integrated device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Control circuit for an integrated device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2192655