Patent
1981-10-01
1986-03-11
Shaw, Gareth D.
H04M 300
Patent
active
045755833
ABSTRACT:
A programmable digital controller has an address matrix memory (20) and an instruction matrix memory (10). The address memory stores address words each having the address of the first sample and the number of samples in a unique group of samples. Unique groups of samples are sequentially stored in an instruction matrix memory. Each column of the instruction memory has data bits for regenerating an instruction set for controlling any one of many apparatus or processes. Each row of the instruction memory has a sample from each instruction set. In response to an enabling signal, the words from the address memory are sequentially read, interpreted, and the samples from the instruction memory caused to be read and for reconstructing the instruction set.
REFERENCES:
patent: 3643226 (1972-02-01), Loizedes et al.
patent: 3979728 (1976-09-01), Reddaway
patent: 4135242 (1979-01-01), Ward et al.
patent: 4168523 (1979-09-01), Chori et al.
AT&T Bell Laboratories
Mills John G.
Nimtz Robert O.
Roberts Patrick E.
Shaw Gareth D.
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