Shared counter arrangement for a digital frequency locked loop t

Details Shared counter arrangement for a digital frequency locked loop t Shared counter arrangement for a digital frequency locked loop t

1982-09-01

1984-11-20

Chin, Tommy P.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

455183, H04N 544, H04B 116

Patent

active

044842210

ABSTRACT:
In a tuning system of a television receiver, the local oscillator (LO) signal and IF picture carrier are selectively coupled to the clock input of the same down counter. The down counter is selectively enabled to count cycles of the LO signal on IF picture carrier during respective LO and IF measurement intervals. A predetermined initial count related to a desired frequency of the LO signal or a predetermined initial count related to a desired frequency of the IF picture carrier are loaded into the down counter during LO and IF presetting intervals which occur just prior to corresponding LO and IF measurement intervals. The counts of the counter at the ends of each of the LO and IF measurement intervals are compared to zero to generate LO and IF error signals representing the frequency deviations, if any, of the LO signal and the IF picture carrier from the respective desired frequencies. The LO and If error signals are utilized to control a tuning voltage for the receiver's tuner.

REFERENCES:
patent: 3961266 (1976-06-01), Tanaka
patent: 4077008 (1978-02-01), Rast
patent: 4084127 (1978-04-01), Tults
patent: 4088959 (1978-05-01), Sumi
patent: 4305157 (1981-12-01), Mogi
patent: 4442547 (1984-04-01), Tults

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