Method of probing a net of an IC at an optimal probe-point

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

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3241581, 364481, 364490, G01R 3128

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active

055303722

ABSTRACT:
Probe-point placement methods are described. A layout description, a netlist description and a cross-reference description of an IC are retrieved from storage. The data structures associate with each net name a list of polygons. Polygons of a selected net are broken into segments of a specified step size. Each segment is evaluated in accordance with a set of prober rules. Values produced by the prober rules are weighted and combined to obtain a prober score for each segment. The prober score indicates suitability of the corresponding net location for probing. If the best prober score indicates an optimal segment exists for probing, the coordinates of that segment are stored and used to direct a probe to the corresponding location of the IC. If the best prober score indicates no optimal segment exists for probing, each segment of the net is evaluated in accordance with a set of probe-point cutter rules. Values produced by the probe-point cutter rules are weighted and combined to obtain a cutter score for each segment. The cutter score indicates suitability of the corresponding net location for cutting a probe-point hole. A segment having the best cutter score is considered optimal for placing a probe point. The methods can be used, e.g., with electron-beam, focused-ion-beam and laser-beam systems, and with mechanical probe systems.

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patent: 5140164 (1992-08-01), Talbot et al.
patent: 5392222 (1995-02-01), Noble
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R. Scharf et al., Layout Analysis and Automatic Test Point Selection for Fast Prototype Debug using E-Beam or Laser-Beam Testsystems, IEEE Custom Integrated Circuits Conference (CICC), 1992, Boston, MA, USA. (month is unavailable).
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