Method of making buried bit line ROM with low bit line resistanc

Details Method of making buried bit line ROM with low bit line resistanc Method of making buried bit line ROM with low bit line resistanc

1994-09-30

1996-06-25

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 67, 437203, H01L 218246

Patent

active

055299431

ABSTRACT:
A ROM array comprises orthogal sets of buried bit lines and polysilicon wordlines. The buried bit lines comprise trenches with insulating material on the side walls, the trenches then being filled with polysilicon. This reduces bit line sheet resistance and increases the punch-through voltage between adjacent bit lines.

REFERENCES:
patent: 4912535 (1990-03-01), Okumura
patent: 5021355 (1991-06-01), Dhong et al.
patent: 5084418 (1992-01-01), Esquivel et al.
patent: 5429973 (1995-07-01), Hong

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