Lay-out structure of power source potential lines and grand pote

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular power supply distribution means

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Details

257691, H01L 2702, H01L 2710, H01L 2348

Patent

active

054422060

ABSTRACT:
Among power supply lines for the standard cells provided nearby the corner part of an outer peripheral power supply line (the grand potential, for example) of a macro cell, the power supply line of the power source potential, for example, is connected to an inner peripheral power supply line (the power source potential) through an auxiliary power supply line provided on said corner part. The auxiliary power supply line is formed in L-shape with the first metal layer line and the perpendicular extending second metal layer line connected each other through a contact. Further, the first metal layer line of the auxiliary power supply line is provided so as to cross over the second metal layer line of the outer peripheral power supply line with an insulating layer therebetween. Therefore, the auxiliary power supply line can connect the inner peripheral power supply line and the power source potential line for the standard cell without electrical contact with the outer peripheral power supply line. Therefore, according to the present invention, all of the power supply lines can be connected each other by the automated lay-out technique without occurrence of short and manual modification, therefore the time course required for semiconductor integrated circuit development can be shortened.

REFERENCES:
patent: 4811073 (1989-03-01), Kitamura et al.
patent: 4989062 (1991-01-01), Takahashi et al.
patent: 5343058 (1994-08-01), Shifter, II
patent: 5391900 (1995-02-01), Onodera et al.
By M. Watanabe, "Very Large Scale Integrated Circuit Design --A Top-down Approach to Custom VLSI-", Sep. 10, 1983, pp. 338-344, Japan, with English translation.

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