Multiprogrammed data processing system with improved interlock c

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G06F 1300, G06F 1516

Patent

active

042143047

ABSTRACT:
A multiprogrammed data processing system with reduced processing time for interlock instructions compares the first partial address contained in a request with a corresponding first partial address of an interlocked address in a first comparator when a main storage control unit receives the request from one of central processing units. The main storage control unit sends the request to a main memory in response to non-coincidence signal from the first comparator.
In response to a coincidence signal from the first comparator, the main storage control unit compares a second partial address contained in the request with a corresponding second partial address of the interlocked address. The main storage control unit sends the request in response to a non-coincidence signal from the second comparator.

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patent: 3761883 (1973-09-01), Alvarez et al.
patent: 3814919 (1974-06-01), Repton et al.
patent: 4050059 (1977-09-01), Williams et al.
patent: 4073005 (1978-02-01), Parkin

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