Topography for sixteen bit CMOS microprocessor with eight bit em

Details Topography for sixteen bit CMOS microprocessor with eight bit em Topography for sixteen bit CMOS microprocessor with eight bit em

1984-11-28

1988-04-19

Williams, Jr., Archie E.

Boots, shoes, and leggings

307468, G06F 100, G06F 944, G06F 1338, H01L 2700

Patent

active

047394757

ABSTRACT:
The topography of a sixteen bit CMOS microprocessor chip including circuitry for enabling it to emulate, under software control, a prior art 6502 microprocessor includes an N-channel minterm logic section including 498 "vertical" diffused minterm lines across which 32 "horizontal" metal lines from an instruction register and a timing generator pass and make selective contact to separate polycrystalline silicon gate electrodes to effectuate a first level of instruction op code decoding. The resulting minterm signals are inverted by a row of CMOS inverters, the outputs of which are connected to polycrystalline lines extending into an N-channel sum-of-minterm section. "Horizontal" metal sum-of-minterm conductors contact various N-channel field effect transistors in the sum-of-minterm region. Those sum-of-minterm lines having fewest field effect transistors connected thereto are positioned on the bottom of the sum-of-minterm array, and those having the most connections to N-channel FETs are positioned at the top thereof to minimize the amount of chip surface area required for the sum-of-minterm array and for routing of the sum-of-minterm signals produced thereby to transfer gate logic on the chip.

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