Constant delay interconnect for coupling configurable logic bloc

Details Constant delay interconnect for coupling configurable logic bloc Constant delay interconnect for coupling configurable logic bloc

1995-04-18

1996-02-06

Trans, Vincent N.

Boots, shoes, and leggings

326 39, 34082583, H03K 17693

Patent

active

054900743

ABSTRACT:
A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. The interconnect network has longlines and programmable interconnect points (PIP's). PIP's are symmetrical distributed in a partially populated fashion within the interconnect network such that a substantially same signal propagation delay develops for each signal routed along a program-selected longline from a CLB adjacent to that longline to an IOB adjacent to that longline.

REFERENCES:
patent: 5212652 (1993-05-01), Agrawal et al.
patent: 5329460 (1994-07-01), Agrawal et al.
patent: 5422823 (1995-06-01), Agrawal et al.

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