Image compressing apparatus

Television – Bandwidth reduction system – Data rate reduction

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348415, H04N 750

Patent

active

054899427

ABSTRACT:
An image compressing apparatus has a predictive coding unit, an orthogonal transform unit, a quantization unit, a variable length coding unit, a coding control unit and a start decision unit. The start decision unit receives predictive errors from the predictive coding unit and a quantization parameter from the coding control unit to produce a start control signal. The start control signal is set to a logic value 1 if the orthogonal transform unit, the quantization unit and the variable length coding unit are to be activated, and to a logic value 0 if they are not to be activated. The orthogonal transform unit, the quantization unit and the variable length coding unit are activated with the logic value 1 to perform respective processes, and are kept unactivated with the logic value 0. The image compressing apparatus is low in power dissipation and short in processing time.

REFERENCES:
patent: 4488174 (1984-12-01), Mitchell
Peter A. Ruetz et al., "A High-Performance Full-Motion Video Compression Chip Set", IEEE Transactions on Circuit and Systems for Video Technology, pp. 111-122, Jun. 1992.
Fujiwara et al., "An All-ASIC Implementation of a Low Bit-Rate Video Codec", IEEE Transactions on Circuit and Systems for Video Technology, pp. 123-133, Jun. 1992.
Yamauchi et al., "Architecture and Implementation of a Highly Parallel Single-Chip Video DSP", IEEE Transactions on Circuit and Systems for Video Technology, pp. 207-220, Jun. 1992.
Yoshimura et al., "A Single Board Video CODEC", NTT R&D No. 8 pp. 1025-1042, 1991.
Hiroshi Yasuda, "International Standards for Multi Coding", Maruzen, pp. 14-18, 84-96 and 125-138.

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