System for improved processor throughput with enhanced cache uti

Details System for improved processor throughput with enhanced cache uti System for improved processor throughput with enhanced cache uti

1996-01-26

1997-12-16

Chan, Eddie P.

395471, 395495, G06F 1208

Patent

active

056995520

ABSTRACT:
A system for interleaving invalidation cycles to a cache memory during those periods when the processor is waiting or has not need to access cache memory. These periods occur during a Read-Miss operation or when bus access delays to main memory cause the processor to wait for receipt of data, or when the processor communicates with network modules other than the cache memory and main memory.

REFERENCES:
patent: 5276852 (1994-01-01), Callandar et al.
patent: 5404483 (1995-04-01), Stamm et al.
patent: 5426754 (1995-06-01), Grice et al.
patent: 5553263 (1996-09-01), Kalish et al.

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