Full adder using transmission gates

Details Full adder using transmission gates Full adder using transmission gates

1983-02-07

1985-12-17

Malzahn, David H.

Boots, shoes, and leggings

307472, G06F 750

Patent

active

045596093

ABSTRACT:
A binary full adder, including provision for carry digits, is implemented using metal-oxide semiconductor field-effect transistors (MOSFET) in the exclusive-OR configuration. The improved structure realizes economies in space occupancy, and device topology, reduction in power requirement and no loss in propagation time over prior full adders employing conventional logic structures.

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patent: 4367420 (1983-01-01), Foss et al.
patent: 4417161 (1983-11-01), Uya
patent: 4471454 (1984-09-01), Dearden et al.
Smith, "Binary Summation Circuit" Technical Notes a Publication of RCA Sep. 1981, 3 Sheets.
Hampel "CMOS/SOS Serial-Parallel Multiplier" IEEE J. of Solid-State Circuits, vol. SC-10, No. 5, Oct. 1975, pp. 307-313.
Varadarajan, "Full Binary Adder Employing Fewer Components" IBM Technical Disclosure Bulletin, vol. 18, No. 9, Feb. 1976, p. 2880.
Digital Logic-Chapter 5, pp. 141 through 149 by Jefferson C. Boyce.

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