Nondestructive read-out dynamic memory cell

Details Nondestructive read-out dynamic memory cell Nondestructive read-out dynamic memory cell

1979-06-29

1981-11-24

Wojciechowicz, Edward J.

357 22, 357 41, 357 42, 357 45, 357 59, H01L 2978

Patent

active

043027644

ABSTRACT:
A MOSFET which is capable of being placed in two states, one of which is quasi-stable and a memory cell which includes such a device is disclosed. The device basically consists of a pair of diffusions of one conductivity type disposed in a substrate of opposite conductivity type. The channel region between the diffusions is ion implanted or diffused with a dopant which forms a channel of the same conductivity type as the diffusions. A gate electrode is spaced from the channel region by a thin oxide and the gate and substrate are biased so that two states of the device are possible. One is a stable, equilibrium or conducting state wherein an opposite conductivity type inversion layer is formed at the surface of the now buried channel. Another state is a quasi-stable, nonequilibrium, nonconductive state wherein the channel region between the diffusions is depleted of mobile charge carriers. This latter state, after a relatively long period of time in the order of several minutes to hours, decays to the stable or conducting state. By applying appropriately poled pulses to the gate or source of the device, the device may be switched from one of the two conducting states to the other. A dynamic memory cell which includes an addressing FET utilizes the device described above. A word line is connected to the gate of an addressing FET which utilizes as its drain the source of the storage device described above while a bit line is connected to the source of the addressing FET. The latter, when rendered conductive by a potential on its gate, applies appropriate write pulses from a pulsed source to place the storage device in one of its two possible states. One embodiment utilizes an annular or enclosed channel device while a memory cell embodiment utilizes an open channel device, the surface of the channel of which is isolated from the substrate by a surrounding recessed oxide (ROX). The channel surface isolation of the storage device is a requirement without which leakage from substrate to the surface would not permit the achievement of the two states of the device. The quasi-stable state remains for a time which is sufficient for most memory purposes and, to the extent that longer times are required, refreshing of the states is available.

REFERENCES:
patent: 3952325 (1976-04-01), Beale et al.
patent: 4053915 (1977-10-01), Cave
IBM-Tech. Bul.-vol. 14, No. 11, Apr. 1972-Forbes et al., pp. 3400-3401.

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