Information storage circuit

Details Information storage circuit Information storage circuit

1975-03-10

1976-09-07

Hecker, Stuart N.

Communications: electrical

Digital comparator systems

307291, G11C 1140, G11C 700

Patent

active

039797350

ABSTRACT:
A non-saturating binary memory cell includes a bistable circuit comprising two cross coupled transistors with an offset resistor connected to their emitters and a third transistor having its collector-to-emitter path connected between the base of one of said two cross-coupled transistors and a data line. Information present on the data line is written into the bistable circuit by passing a turn on current through a first diode in a direction to forward bias the base of said third transistor. The writing of information into the bistable circuit is selectively inhibited by means of a diode network connected to prevent the forward biasing of said third transistor.

REFERENCES:
patent: 3761898 (1973-09-01), Pao
RCA Linear Integrated Circuits, 8/70, pp. 4, 5, 9.
Moore, Storage Cell With Single Single Bit Line, IBM Technical Disclosure Bulletin, vol. 14, No. 6, 11/71 p. 1693.
Bleher et al., Accessing Circuit for Memory Cell, IBM Technical Disclosure Bulletin, vol. 14, No. 9, 2/72, pp. 2821-2822.
Moore, et al., Fast NDRO Memory Circuits for Integration, IBM Technical Disclosure Bulletin, vol. 14, No. 6, 11/71 p. 1666.
Bodendorf et al., Polarity-Hold Circuit with True and Complement Output, IBM Technical Disclosure Bulletin, vol. 14, No. 2 7/71, p. 416.
Berding, Simultaneous Read-Write Monolithic Storage Cell, IBM Technical Disclosure Bulletin, vol. 13, No. 3, 8/70, p. 620.
Wo, Flip-Flop with Subcollector Interconnections, IBM Technical Disclosure Bulletin, vol. 14, No. 6, 11/71, p. 1682.

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