Time base converter employing two reference position phase lock

Details Time base converter employing two reference position phase lock Time base converter employing two reference position phase lock

1988-01-12

1989-01-03

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 70, H04J 400

Patent

active

047962534

ABSTRACT:
A time base converter employs a two position, phase lock loop (40) to write twice orthogonally spaced signals into a split phase memory (34), which in turn can be read out at the timing rate of an incorporating communications system. The converter effectively converts the time base of signals read out of a demodulator (14) to the system time base, thus permitting use of the demodulator in computer based, digital processing systems. Readout of the signals is facilitated by a pair of marker tones f.sub.H, f.sub.L which are introduced into the signal on the upper and lower sides of the input bandwidth. The signal is digitized by A/D converters (28, 30) and the resulting data is employed to drive the phase lock loop. The phase lock loop includes a counter (44) driven by a voltage controlled oscillator (46) which time shares a pair of loop filters (52, 54) that respectively pass the marker tones f.sub.H, f.sub.L. The counter is clocked at the orthogonal timing rate such that the demodulated data signals are read out on even counts and the marker tones are sampled on odd counts. A controller (38) forms a pair of gates for sampling the marker tones and the phase lock loop servos to the center of each gate time.

REFERENCES:
patent: 4304000 (1981-12-01), Bonnerot et al.
patent: 4312062 (1982-01-01), Bellanger et al.
"Design of Digital Signal Processor in a TDM/FDM Transmultiplexer", ICC 80' International Conf. on Comm. Seattle, WA, 8-12, Jun. 80; pp. 42.2.1-47.2.6.

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