Fishing – trapping – and vermin destroying
Patent
1987-09-08
1989-01-03
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437176, 437184, 437188, 437912, 357 15, 357 51, 357 22, H01L 21265, H01L 2144, H01L 2148
Patent
active
047957174
ABSTRACT:
A semiconductor device with a FET utilizing a two-dimensional electron gas (2DEG), including a substrate, a first semiconductor layer (an undoped GaAs layer) formed on the substrate by an MBE method, a second semiconductor layer (an n-type AlGaAs layer) formed on the first layer by an MBE method, a source electrode and a drain electrode formed on the second layer and having alloyed regions, and a gate electrode formed on the second layer. To decrease the contact resistance between the alloyed regions and the 2DEG layer in the first layer, impurity doped regions are formed in the first layer under the source electrode and the drain electrode by an ion-implantation method, prior to the formation of the second layer. Further, an internal conductive line or resistor can be formed by doping impurities into the first layer by an ion-implantation method prior to the formation of the second layer.
REFERENCES:
patent: 4194935 (1980-03-01), Dingle et al.
patent: 4310570 (1982-01-01), Calviello
patent: 4338616 (1982-07-01), Bol
patent: 4377030 (1983-03-01), Pettenpaul et al.
patent: 4396437 (1983-08-01), Kwok et al.
patent: 4424525 (1984-01-01), Mimura
patent: 4434013 (1984-02-01), Bol
patent: 4467519 (1984-08-01), Glang et al.
patent: 4663643 (1987-05-01), Mimura
Lehovec et al, "Analysis of GaAs FET's for Integrated Logic," IEEE Transactions on Electron Devices, vol. ED-27, No. 6, Jun. 1980, pp. 1085-1086.
Chang, "Self-Aligned MESFET Structure", IBM Technical Disclosure Bulletin, vol. 24, No. 8, Jan. 1982, pp. 4071-4072.
Abe et al., "Advanced Device Technology for High Speed GaAs VLSI", Solid State Devices 1982, ESSDERC-SSSDT Meeting at Munich, 13th-16th Sept. 1982, pp. 25-50.
Sze, VLSI Technology, Bell Telephone Laboratories, Inc., 1983, pp. 391-397.
Ghandhi, VLSI Fabricaiton Principles, John Wiley and Sons, Inc., 1983, pp. 330-337.
Fujitsu Limited
Hearn Brian E.
Wilczewski M.
LandOfFree
Method for producing semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for producing semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for producing semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2168361