Patent
1995-06-06
1997-06-17
Gossage, Glenn
3954211, 395411, 395308, G06F 1210, G06F 1200
Patent
active
056405286
ABSTRACT:
A method and apparatus for translating a first address in a first address space, such as a processor address space, to a second address in a second address space, such as a system address space, are described. Data alignment signal determinations based on comparisons between destination and source addresses permit automatic replacement of virtual addresses with actual physical addresses to permit direct data transfer between devices. In one embodiment, the apparatus for translating comprises a processor; a page table having a mask register, a comparison value register, and a replacement value register; and a comparator coupled to the comparison value register and to the replacement value register. A programmable mask within the translation mask register is employed to partition a virtual address. A first subaddress comprises a subset of the bits of the first address and a second subaddress comprises remaining bits of the first address. The first subaddress is masked with a programmable mask value in the translation mask register and is compared by the comparator with successive comparison values in the comparison value register until a match comparison value is found. A programmable replacement value in the replacement value register corresponding to the match comparison value is concatenated with the second subaddress. The programmable replacement values, which correspond to programable map windows, permit the programmable mapping of virtual addresses into different predetermined regions of system virtual address space.
REFERENCES:
patent: 4800489 (1989-01-01), Moyer et al.
patent: 4860192 (1989-08-01), Sachs et al.
patent: 4920483 (1990-04-01), Pogue et al.
patent: 5282274 (1994-01-01), Liu
Harney Kevin
Sprague David L.
Gossage Glenn
Intel Corporation
Kinsella N. Stephan
Murray William H.
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