Synchronization circuit capable of establishing synchronism even

Details Synchronization circuit capable of establishing synchronism even Synchronization circuit capable of establishing synchronism even

1985-10-30

1987-09-08

Griffin, Robert L.

Pulse or digital communications

Spread spectrum

Direct sequence

328 63, 307527, H04L 700

Patent

active

046929312

ABSTRACT:
In a synchronization circuit for use in demodulating an input signal carrying a transmission data signal at a symbol rate, a sampling circuit samples the input signal at a predetermined sample rate which may be different from the symbol rate, to produce a sequence of sampled signals. The sampled signal sequence is interpolated by the use of an interpolator into first and second partial interpolated signals which have different phases from each other. The first and second partial interpolated signals are processed by a processing circuit to produce timing errors between the first partial interpolated signals and the sampled signal sequence. The processing circuit controls the phases of the first and second partial interpolated signals with reference to the timing errors so that the both partial interpolated signals are derived at predetermined points of the sampled signal sequence. On reception of the transmission data signal of a multi-level divisible into a plurality of bits, the interpolator comprises a plurality of elementary interpolators for interpolating the respective bits to produce fragmentary interpolated signals. The fragmentary interpolated signals are combined into the interpolated signal sequence. The elementary interpolators may be controlled by two internal samplers in consideration of the timing errors.

REFERENCES:
patent: 4032847 (1977-06-01), Unkauf
patent: 4165488 (1979-08-01), Guidoux et al.
patent: 4308618 (1981-12-01), Levy et al.
patent: 4321705 (1982-03-01), Namiki
patent: 4376309 (1983-03-01), Fenderson et al.
patent: 4416017 (1983-11-01), Jasper et al.
patent: 4453259 (1984-06-01), Miller

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