Semiconductor memory test system

Details Semiconductor memory test system Semiconductor memory test system

1987-05-19

1989-05-30

Smith, Jerry

Excavating

371 21, G06F 1100

Patent

active

048357740

ABSTRACT:
In a semiconductor test system, higher accuracy testing of semiconductor memories is achieved by providing test data from a modified pattern generator to identical addresses in both the memory under test and a buffer memory. This is achieved for various types of semiconductor memories by treating data generated by the modified pattern generator for the memory under tests in ways that would correspond to how the data is treated in various memories to be tested before storing the data in the buffer memory. This is accomplished using a variety of multiplexers and counters under control of a control signal generator. Data stored at locations with the same address in both memories is read out for comparison in a logic comparator. If the data is not identical, the semiconductor memory under test is rejected as defective.

REFERENCES:
patent: 3544777 (1970-12-01), Winkler
patent: 4369511 (1983-01-01), Kimura
patent: 4370746 (1983-01-01), Jones

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