Processor including fetch operation for branch instruction with

Details Processor including fetch operation for branch instruction with Processor including fetch operation for branch instruction with

1984-10-31

1988-10-04

Williams, Jr., Archie E.

Boots, shoes, and leggings

G06F 1202

Patent

active

047759275

ABSTRACT:
A method and apparatus expands the capability of an instruction prefetch buffer. The method and apparatus enables the instruction prefetch buffer to distinguish between old prefetches that occurred before a branch in an instruction stream and new prefetches which occurred after the branch in the instruction stream. A control tag is generated each time a request for an instruction is sent to a storage. The returning instruction has appended thereto the original control tag which is then compared to the current value of control tag in the instruction prefetch buffer. If the two values match, then this is an indication that a branch has not occurred and the instruction is still required. However, if the two values of the control tag are not equal, then this is an indication that a branch in the instruction stream has occurred and that the instruction being sent from storage to the buffer is no longer required. The method and apparatus are also applicable to the use of branch-with-execute instructions wherein a subject instruction is executed immediately following the branch-with-execute instruction. The execution of this subject instruction before the branch target instruction enables the system processor to continue operating while it is waiting for the branch target instruction.

REFERENCES:
patent: 4155120 (1979-05-01), Keefer et al.
patent: 4179737 (1979-12-01), Kim
patent: 4348724 (1982-09-01), Cushing et al.
patent: 4360868 (1982-11-01), Retter
patent: 4409654 (1983-10-01), Wada
patent: 4430706 (1984-02-01), Sand
patent: 4435756 (1984-03-01), Potash
patent: 4471433 (1984-09-01), Matsumoto
IBM TDB vol. 24, No. 10, Mar. 1982, pp. 4986 to 4987, "Synchronous LSSD Packet Switching Memory and I/O Channel", by Jeremiah et al.
IBM TDB vol. 25, No. 3B, Aug. 1982, pp. 1771 to 1772, "Exact Interrupt Capability for Processors Using a Packet-Switching Storage Channel", by Hester et al.

Affiliated with

Also associated with

Rating

Processor including fetch operation for branch instruction with does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Processor including fetch operation for branch instruction with , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor including fetch operation for branch instruction with will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2159065