Folder Bitline DRAM having access transistors stacked above tren

Details Folder Bitline DRAM having access transistors stacked above tren Folder Bitline DRAM having access transistors stacked above tren

1992-11-13

1994-08-09

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

053366298

ABSTRACT:
A folded bitline DRAM cell is described which includes a trench capacitor and a planar-configured access transistor. The access transistor is stacked over the capacitor and has a first terminal connected thereto. The access transistor includes a planar-oriented gate. A first wordline has a minor surface in contact with the gate and a major surface that is oriented orthogonally to the gate. An insulating pedestal is positioned adjacent the gate and a passing wordline is positioned on the pedestal, the passing wordline having a major surface parallel to the first wordline. In another embodiment, the folded bitline DRAM cell includes a vertically oriented access transistor having one terminal formed on the upper extent of a contact to the trench capacitor, to provide optimum electrical connection thereto.

REFERENCES:
patent: 4649625 (1987-03-01), Lu
patent: 4734384 (1988-03-01), Tsuchiya
patent: 4920065 (1990-04-01), Chin et al.
patent: 5181089 (1993-01-01), Matsuo et al.

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