Radiation imagery chemistry: process – composition – or product th – Registration or layout process other than color proofing
Patent
1998-09-01
2000-12-12
Young, Christopher G.
Radiation imagery chemistry: process, composition, or product th
Registration or layout process other than color proofing
430 30, 430296, 430328, 430942, G03F 900
Patent
active
061596442
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a method of fabricating semiconductor circuit devices, and more particularly, to a method of fabricating semiconductor circuit devices which makes it possible to enhance an alignment at the time of making, in an exposure method, a mixed use of a reduction image projection exposure by means of ultraviolet rays and an electron beam drawing method.
BACKGROUND ART
With semiconductor circuit devices being highly integrated, they are getting more and more microminiaturized. In particular, in a recent large-scale integrated circuit (LSI), dimensions of interconnections of the devices or a dimension of a perforation called a hole, which passes through an interlayer between the devices, have been becoming 0.3 .mu.m or less. This requires that processes of fabricating the semiconductor circuit devices and apparatuses for fabricating thereof also respond to the high integration and the microminiaturization.
Of the processes of fabricating the semiconductor circuit devices, in an exposure process in which the reduction image projection exposure with ultraviolet rays as a light source has been mainly employed up to now, the response to the microminiaturization has been made through an enhancement in the image resolution achieved by wave shortening of the light source. Unfortunately, for a dimension of 0.3 .mu.m or less, even the wave shortening of the light source has already approached its limit. Developed accordingly is a technique which aims at exceeding the prior art resolution limit through an employment of a phase-shift mask or a modified illumination. For a hole pattern at 0.2 .mu.m level, however, it is difficult to resolve the image with the use of the existing optical exposure techniques.
Meanwhile, under study is an employment, at a mass production level, of an exposure method in which an electron beam is used. The electron beam exposure, which is superior in the image resolution, makes it possible to easily form the hole pattern at 0.2 .mu.m level. However, a prior art exposure method by means of the electron beam is an exposure method based on so-called a one-stroke drawing in which a spot beam or a variable shaped beam is used. This made the throughput 1/10th or less as compared with the optical exposure in which a reduction image projection exposure apparatus is used, thus decreasing the number of wafer sheets exposed per unit of time. For this reason, the employment was not common in the mass production fabrication of the LSIs. In recent years, however, an enhancement in wafer processing time has been achieved in the electron beam drawing method, too, through development of a method such as a cell projection method or a block exposure which allows a range for about 5 .mu.m angle to be exposed at a time. Thus, the employment in the mass production fabrication is under study.
Then, performed is a study of a method in which, in the exposure process of the processes of fabricating the semiconductor circuit devices, a prior art reduction image projection exposure using as a light source i-rays, KrF excimer laser, and so on and the electron beam exposure are in a mixed use and are selectively employed for each layer, thus making it possible to respond to the high integration and the microminiaturization of the semiconductor. In particular, a hole layer, the image of which is difficult to resolve by means of light, allows a fewer number of drawing shots to be performed in the electron beam exposure as compared with other layers such as interconnections, thus bringing about a higher throughput. On account of this, from the viewpoint of the productivity, too, it is considered to be effective to use the electron beam exposure in the hole layer.
There are a plurality of processes in the exposure process of the processes of fabricating the semiconductor circuit devices, and patterns are superposed in each exposure process on a wafer so as to form the semiconductor circuit devices. Specified is a relative position of upper and lower patterns between the exposed la
REFERENCES:
patent: 5989759 (1999-11-01), Ando et al.
Nakayama Yoshinori
Ohta Hiroya
Okumura Masahide
Saitou Norio
Satoh Hidetoshi
Hitachi , Ltd.
Young Christopher G.
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