System for guaranteed CPU bus access by I/O devices monitoring s

Details System for guaranteed CPU bus access by I/O devices monitoring s System for guaranteed CPU bus access by I/O devices monitoring s

1992-04-17

1995-08-22

Lee, Thomas C.

Boots, shoes, and leggings

395865, 3642405, 3642426, 36424292, 364DIG1, G06F 1336

Patent

active

054448557

ABSTRACT:
A method and system for controlling access to a system bus in a computer system is provided. The system devices include a central processing unit, a memory controller for controlling access to system memory, and at least one input/output device having a coprocessor incorporated therein. The system bus electrically connects the system devices. Any one of the system devices may serve as a bus master of the system bus at any one time when communicating over the bus with each other or with system memory. Each of the at least one input/output device incorporates control logic therein for (i) monitoring bus activity to calculate the bus mastering time during which the memory controller and the at least one input/output device control the bus, and (ii) outputting an inhibit signal which denies access to the bus by the at least one input/output device if the calculated bus mastering time is equal to or greater than a predetermined bus mastering time period.

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Belady et al, "Time-Dependent Data-Locking Mechanism" Apr. 1977, IBM Technical Disclosure Bulletin, pp. 4485-4486.

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