Memory device providing burst read access and write access from

Details Memory device providing burst read access and write access from Memory device providing burst read access and write access from

1998-06-12

1999-11-02

Phan, Trong

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, G11C 800

Patent

active

059783036

ABSTRACT:
According to a first aspect of the invention, a memory device has a main memory array and a sub memory array. In a single burst, data are read from a series of columns in the main memory array, transferred from one column in the main memory array to one column in the sub memory array, read from a series of columns in the sub memory array, and written into the above-mentioned one column in the main memory array. According to a second aspect of the invention, a memory device has a memory array and separate external data input terminals and output terminals. In a single burst, data are read from a series of columns in the memory array, and written to one of the columns, preferably the last column in the series. Input of the written data is preferably simultaneous with the output of the data read from the column to which the input data are written.

REFERENCES:
patent: 5604697 (1997-02-01), Takahashi et al.
patent: 5848021 (1998-12-01), Sugibayashi
MSM54V24632A 131,072 Word.times.32-Bit.times.2-Bank Synchronous Dynamic RAM, Oki Semiconductor, Aug. 1, 1997, pp. 1-29.

Affiliated with

Also associated with

Rating

Memory device providing burst read access and write access from does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory device providing burst read access and write access from , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device providing burst read access and write access from will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2144927