Error-correcting encoder, error-correcting decoder, and data tra

Details Error-correcting encoder, error-correcting decoder, and data tra Error-correcting encoder, error-correcting decoder, and data tra

1995-02-07

1997-12-16

Baker, Stephen M.

Excavating

371 376, H03M 1300

Patent

active

056993684

ABSTRACT:
The present invention provides an error-correcting encoder and an error-correcting decoder which encode/decode a plurality of information symbols in parallel with a reduced number of shifts, which enables a reduction in the processing time. The error-correcting encoder of the invention includes a shift-register including stages equal to a predetermined number of check symbols for inputting different information symbols in parallel from a plurality of input terminals. The encoder also includes a Galois field multiplier for multiplying each coefficient and a Galois field adder to obtain the predetermined number of check symbols from the information symbols. The encoder can generate the predetermined number of check symbols with shifts, the number of which is reduced according to the number of parallel inputs. The syndrome generator of the error-correcting decoder of the invention includes a plurality of Galois field multipliers which multiply the coefficients for calculating syndromes for inputting different code symbols in parallel from a plurality of input terminals. The syndrome generator also includes a Galois field adder and a shift-register(s) to obtain the predetermined syndrome generating polynomial. The syndrome generator can obtain the desired syndromes with shifts, the number of which is reduced according to the number of parallel inputs.

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Tomoko Matsushima "A Design of a High-Speed Reed-Solomon Codec LSI" pp. 103-106.
N. Glover et al., "Practical Error Correction Design for Engineers", 2nd ed., Data Systems Technology Corp., pp. 49, 50, 243-249, Aug. 1988.

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